1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors comprising sigma-shaped embedded semiconductor materials, such as embedded semiconductor alloys, so as to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element for complex circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology is the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In MOS circuits, field effect transistors, i.e., P-channel transistors and/or N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using MOS technology, transistors are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions so as to provide low sheet and contact resistivity in combination with desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for maintaining high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby enabling a performance improvement that is comparable with the advance to a technology standard requiring extremely scaled critical dimensions, while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since strained silicon may be considered as a new type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium material next to the channel region so as to induce a compressive stress that may result in a corresponding strain. When forming the silicon/germanium material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Generally, this approach results in a significantly improved transistor performance of P-channel transistors since drive current capability and switching speed are enhanced. Generally, the effect of the strain-inducing mechanism provided by the embedded silicon/germanium alloy strongly depends on the material composition of the silicon/germanium alloy, i.e., on the germanium concentration, since an increased amount of germanium in the alloy results in a greater lattice mismatch between the natural lattice constant of silicon/germanium and the lattice constant of the silicon base material. On the other hand, according to presently available selective deposition recipes for forming the silicon/germanium alloy, the germanium concentration may not be arbitrarily increased, since significant lattice defects may be created, thereby offsetting the advantages that should be obtained by providing the silicon/germanium alloy in a highly strained state. Consequently, in other approaches, the efficiency of the strain-inducing mechanism is increased for a given germanium concentration of the alloy by appropriately dimensioning the cavity that is formed laterally adjacent to the gate electrode structure, thereby increasing the amount of strained material that may finally act on the adjacent channel region. Moreover, the lateral offset or generally the proximity of the strained silicon/germanium alloy to the channel region may also significantly affect the finally achieved strain conditions in the channel region so that, in sophisticated approaches, it is attempted to continuously reduce the lateral offset of the cavities and thus of the silicon/germanium alloy from the channel region. To this end, appropriate etch techniques may be applied in combination with appropriate protective liner materials provided at sidewalls of the gate electrode structures in order to further reduce the lateral offset of the resulting cavities.
In still other developments with respect to enhancing performance of sophisticated semiconductor devices, the well-established gate materials silicon dioxide or silicon oxynitride and polysilicon are increasingly replaced by sophisticated material systems since typically a reduction of the gate length of field effect transistors may require a corresponding adaptation of the capacitive coupling of the gate electrode to the channel region, which has been conventionally achieved by further reducing the silicon dioxide-based gate dielectric material. With a thickness of less than 2 nm in sophisticated field effect transistors having a gate length of 50 nm and less, however, the leakage currents through the thin gate dielectric material may reach values that may no longer be compatible with the power consumption requirements and heat dissipation capabilities of many types of complex circuits. Therefore, the silicon dioxide-based gate dielectric materials are increasingly replaced by so-called high-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of 10.0 and higher. For example, a plurality of metal oxides and silicates, or combinations thereof, such as hafnium oxide and the like, may be used, possibly in combination with an extremely thin conventional dielectric material, in order to provide the high capacitive coupling, while restricting the resulting gate leakage currents to an acceptable level. Similarly, the polysilicon material may be replaced, at least at the vicinity of the sophisticated high-k dielectric material in order to enable an appropriate adaptation of the work function and thus threshold voltage, thereby also enhancing performance as, for instance, the formation of any depletion zone, as is typically the case in sophisticated polysilicon-based devices, may be avoided while also superior conductivity of a corresponding replacement material, such as titanium nitride, possibly in combination with work function adjusting metal species, may be achieved.
In sophisticated applications, frequently providing a superior gate electrode structure on the basis of a high-k dielectric material and the incorporation of a strain-inducing semi-conductor alloy, such as silicon/germanium, are combined in order to further enhance overall performance of the transistors. Upon further device scaling, however, the efficiency of, in particular, the strain-inducing mechanism may be less pronounced or may even contribute to significant variations in transistor characteristics, which is caused by process variations upon forming corresponding cavities in close proximity to the sophisticated gate electrode structures and subsequently selectively growing the silicon/germanium alloy therein. It has been recognized that generally a superior encapsulation of the gate electrode materials and the gate dielectric material has to be ensured, in particular when sophisticated high-k metal gate electrode structures are formed, since the reactive process atmospheres which have to be established upon forming the cavities and growing the silicon/germanium alloy may result in a certain degree of material erosion, which in turn may result in corresponding variations of transistor characteristics, such as threshold voltage and the like. Thus, any protective materials, such as silicon nitride liners and the like, which may typically be provided on sidewalls of sophisticated gate electrode structures may not be reduced in thickness to an extent as would be desirable in view of increasing the efficiency of the strain-inducing effect of the embedded silicon/germanium alloy. That is, reducing the thickness of any protective sidewall spacer material, and thus reducing the lateral offset of the embedded silicon/germanium material, may unduly influence the overall transistor behavior so that pronounced variations during the transistor operation may be observed, thereby making the approach of reducing thickness of any protective sidewall spacers less than desirable.
Therefore, other approaches have been contemplated in which well-controllable etch strategies are applied, which may allow reducing the lateral offset while at the same time ensuring integrity of the sensitive gate materials. For example, it is well known that a plurality of wet chemical etch recipes may result in a crystallographically anisotropic etch behavior, in which a certain type of crystal planes may act as efficient etch stop planes which, when exposed during the etch process, may significantly slow down the advance of the material removal process, while, in other crystal corrections, the etch process may advance with the desired high etch rate. Depending on the basic crystallographic configuration of the semiconductor material, therefore, well-defined etch conditions may be achieved, which may have a self-limiting lateral etch behavior, for instance for a standard silicon configuration with a (100) crystal plane as a surface plane and a (110) axis oriented along the current flow direction in the corresponding channel regions. In this manner, the (111) crystal planes may act as etch stop planes. Although the approach of using crystallographically anisotropic etch techniques represents a promising approach for defining the dimensions and the shape of the cavities in a well-controllable manner, it turns out, however, that, upon further device scaling, a significant variation of the dimensions of the resulting cavities may be observed, as will be explained in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a semiconductor layer 102, such as a silicon layer. The semiconductor layer 102 typically comprises a plurality of active regions, which are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience, a single active region 102A is illustrated in FIG. 1a. Furthermore, a gate electrode structure 160 is formed on the active region 102A and comprises a gate dielectric material 161, an electrode material 162, a dielectric cap layer or layer system 163 and a protective spacer or spacer structure 164. As discussed above, the gate electrode structure 160 may represent a sophisticated high-k metal gate electrode structure, wherein the gate dielectric material 161 may include a high-k dielectric material, while the electrode material 162 may comprise metal-containing electrode materials, work function metals and the like, in order to adjust the transistor characteristics. In other cases, sophisticated polysilicon/silicon dioxide-based electrode structures are provided, wherein also superior integrity, at least at the vicinity of the gate dielectric material 161, is to be ensured since typically, even for conventional dielectric materials, the extremely reduced thickness may require avoiding any undue exposure to any reactive process atmospheres during the further processing of the device 100. Consequently, a reliable confinement of the materials 161 and 162 is required and is accomplished by means of the dielectric cap layer 163 and the spacer 164, which may be comprised of any appropriate material, such as silicon nitride, silicon dioxide and the like. Furthermore, as discussed above, in sophisticated semiconductor devices, a length of the gate electrode structure 160, i.e., in FIG. 1a, the horizontal extension of the electrode material 162, may be 50 nm or even 40 nm and less.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of complex process strategies including the formation of any isolation regions (not shown), followed by the formation of appropriate materials so as to provide a gate layer stack, which is subsequently patterned by using sophisticated lithography and etch techniques. In this manner, the layers 161, 162 and 163 may be formed with appropriate lateral dimensions in accordance with the design rules. Thereafter, the spacer or spacer structure 164 is formed, for instance, by depositing one or more material layers, such as silicon nitride materials and the like, and patterning these layers, at least above the active region 102A, in order to form the spacer structure 164. Thus, as indicated by the dashed lines, cavities 103 are to be formed in the active region 102A in order to form therein a strain-inducing silicon/germanium alloy. As discussed above, the cavities 103 may have a cross-sectional shape that may also be referred to as sigma shaped, since, at least at a side towards a channel region 152, inclined sidewall surface areas may border the cavities 103, wherein the sidewalls may substantially correspond to specific crystal planes, such as (111) planes for a silicon material.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. For example, in some approaches, a recess 103R is formed in the active region 102A in order to provide a certain degree of under-etching of the cavity 103 during a subsequent crystallographically anisotropic etch process. Thus, by adjusting the depth of the recess 103R, generally the size and shape of the cavity 103 during the subsequent etching can be determined. To this end, well-established plasma-based etch recipes may be applied so as to etch silicon material selectively with respect to, for instance, silicon dioxide, silicon nitride and the like.
After the etch process for forming the recess 103R, however, the device 100 may have to be exposed to various process atmospheres, such as the ambient atmosphere and the like, wherein exposure time may significantly vary since typically the scheduling of the manufacturing flow in a complex semiconductor facility may be rather complex so that, for various types of products, or even for the same time of product, and different substrates, differing queue times associated with the various processes may be encountered. Consequently, usually an oxide layer 104 may form on exposed surface areas 103S of the recess 103R after the plasma-based etch process for forming the recess 103R and any further processes required for forming the cavity 103 in its final desired shape.
FIG. 1c schematically illustrates a cross-sectional view of a typical sequence of etch processes, which are applied so as to form the cavities 103 in their desired sigma-shaped configuration. As shown, in a first etch process 105, the oxide layer 104 (FIG. 1b) is removed on the basis of appropriate etch chemistries, such as hydrofluoric acid, in order to prepare the device 100 for a subsequent crystallographically anisotropic etch process 106. To this end, any appropriate etch chemistry, such as TMAH (tetra methyl ammonium hydroxide) or any other hydroxide chemistries may be applied, wherein many of these chemistries may have a high selectivity with respect to silicon dioxide, silicon nitride and the like. Generally, the high selectivity during a corresponding crystallographically anisotropic etch process 106 is desirable, for instance in view of gate integrity and the like. On the other hand, any oxide residues which may not be entirely removed during the etch process 105 may result in a significant reduced etch rate during the etch process 106. In the example shown in FIG. 1c, it may be assumed that the device 100 receives the cavity 103 so as to substantially correspond to the target size that a depth 103D and a lateral extension below the gate electrode structure 160, indicated by 103L, may be within a valid range.
FIG. 1d schematically illustrates the situation during the etch sequence 105, 106 for a semiconductor device 100A, which may be a device formed on the same substrate as the device 100, however at a very different position, or the device 100A may represent a device formed on a different substrate having experienced a different queue time prior to performing the etch process 105. As shown, upon using predetermined process parameters of the process 105, a thin oxide layer 104 may still be formed on the surface areas of the recess 103R which, however, may have a significant influence during the subsequent crystallographically anisotropic etch process 106. That is, due to the high selectivity of the etch chemistry used for different process parameters during a very long initial phase of the process 106, the oxide layer 104 has to be removed so that, during the resulting etch time, the cavity 103 is provided with reduced size, as indicated by the reduced depth 103D and/or the reduced lateral extension 103L.
Consequently, due to any process non-uniformities occurring across individual substrates and also across a plurality of substrates caused by scheduling non-uniformities and process related non-uniformities, the further processing of different semiconductor devices is continued on the basis of the cavities 103 having different size, which may thus result in significantly different transistor characteristics, as is also described above. Consequently, although the approach of using the crystallographically anisotropic etch process 106 is in principle very promising, it turns out, however, that nevertheless a pronounced variability of transistor characteristics is observed.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which an embedded semiconductor material may be formed in active regions of transistors, avoiding or at least reducing the effects of one or more of the problems identified above.